vom 04.08.2026
For an innovative automotive semiconductor project in the braking systems domain, we are looking for an experienced Senior Digital Verification Engineer who can take ownership of the verification of safety-critical ASIC IPs and contribute immediately to a tape-out-critical project.
Responsibilities: Own the verification of complex ASIC IP blocks from specification review to verification sign-off. Analyze requirements and derive comprehensive verification plans. Develop and extend SystemVerilog/UVM verification environments. Create reusable verification components, scoreboards and reference models. Develop constrained-random and directed test cases. Write SystemVerilog Assertions (SVA). Verify functional behavior, diagnostics and fault scenarios. Drive functional and code coverage closure. Debug verification issues together with RTL, analog and system architects. Support verification reviews and final sign-off activities.
Requirements: 8+ years of ASIC or SoC Digital Verification experience. Excellent knowledge of SystemVerilog and UVM. Strong experience with coverage-driven verification methodologies. Experience creating verification plans directly from specifications. Development of scoreboards, reference models and reusable verification components. Strong debugging skills (e.g. Verdi, DVE, SimVision or similar). Experience with SystemVerilog Assertions (SVA). Excellent English communication skills.
Location: South Germany (Hybrid / On-site depending on project requirements). Start: September 2026. Duration: 3 months (with potential follow-up opportunities)
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